A Jitter Estimation Method for Cascaded Programmable PLLs

In a phase-locked loop (PLL), it is critical to understand how reference clock noise affects the output quality, particularly in applications where PLLs are cascaded. That is, where the output of one PLL serves as the reference clock for another PLL. Traditionally, this problem is solved by qualitative analyses, rules of thumb, and simulation, all of which require confirmation with measurements. We present a characterization technique that quantifies and predicts the transfer of reference clock noise to the PLL output, without requiring a circuit model. We will present theory, data, and measurement correlations, as well as application examples. Author Biographies Dr. Daniel Chow is a senior member of technical staff in the characterization group at Altera Corporation. His responsibilities include testing and validation of high-speed components. Specifically, he is responsible for developing Altera’s knowledge base on jitter measurement issues. Dr. Chow received his Ph.D. from the University of California, Davis. Mr. Vincent Tsui is an advanced engineer in the characterization group at Altera Corporation. He is responsible for characterizing Altera's high-speed transceiver products. Mr. Tsui received his B.S. and M.S. degrees in computer and electrical engineering from the University of California, Davis. Mr. San Wong is a senior manager in the characterization group at Altera Corporation. His current responsibilities include test automation, transceiver characterization, simultaneous switching noise, system-level verification and other signal integrity solutions. He received his B.S. in physics from the University of California, Berkeley and his M.S. in Electrical Engineering from Stanford University. 1. Background and Motivation In typical phase-locked loop (PLL) applications, excessive noise in the PLL output is generally undesirable. Typically, the main concern surrounds timing noise, expressed as phase noise in the frequency domain or jitter in the time domain. Noise can come from internal components of the PLL or external sources such as the reference clock or power supply. From an application perspective, it is important to understand how reference clock noise affects the output quality of the PLL. This is particularly important in applications where PLLs are cascaded. That is, the output of one PLL serves as the reference clock for another PLL. In these applications, jitter accumulates from one PLL to another. If the jitter is excessive, a PLL at a later stage will lose its lock. Traditionally, there is no comprehensive method to characterize this type of noise transfer. Often, engineers rely on qualitative assessments, general rules of thumb, and simulations to tackle this challenge, all of which require confirmation with measurements. The transceiver characterization team at Altera has developed a novel technique to quantitatively predict the transfer of noise from a reference clock to the PLL output without requiring a circuit model. The reference clock may be a laboratory clock generator, crystal oscillator, or another PLL. This methodology is immediately applicable to engineers concerned with noise issues in PLL applications. 2. PLL Noise Theory Much research has been dedicated to the modeling of noise in PLLs [1, 2]. Figure 1 shows a PLL block diagram consisting of a reference clock, phase detector, charge pump, loop filter, voltage controlled oscillator (VCO), and loop divider. Under normal operation, the PLL output frequency (fOut) is the product of the reference clock frequency (fRef) and the loop divider value. Typical models assume that every component in the PLL has an associated intrinsic noise power and gain. In closed loop operation, all of the intrinsic noise powers and gains interact to create the total noise at the PLL output. Phase Detector Charge Pump Loop Filter VCO Loop Divider Ref Clk Output Figure 1: Block diagram for PLL components. The intrinsic noise power and gain of the individual components are often difficult (if not impossible) to characterize. Some components can be simulated, but this still requires correlation with measurements. Therefore, it is extremely challenging to build an accurate PLL noise model from its components. Since the primary concern in most applications is the jitter output of the PLL, we propose a method to predict PLL output jitter based on laboratory measurement and characterization of the PLL’s intrinsic properties. The advantage of this method is that the PLL is treated as a system, rather than as a collection of individual components. For a PLL in locked operation with small phase errors, the noise behavior of the components shown in Figure 1 can be lumped together to form a linear PLL noise transfer model, shown in Figure 2. The noise power of the reference clock is denoted as PRef. The noise power of the PLL output is POut. All components inside the PLL collectively behave as an intrinsic system noise power (PInt) and a closed-loop gain (G). Note that PRef, PInt, POut, and G are all frequency-dependent parameters. PLL (Pint, G) PRef POut Figure 2: Block diagram for PLL system noise model. From this model, for any frequency, the PLL output noise power is simply the reference clock noise power amplified by the closed-loop gain plus the PLL intrinsic noise power, expressed as ( ) ( ) ( ) ( ) f P f G f P f P Int Ref Out + × = . Eq. 1 The noise powers PRef and POut correspond to the stimulus and response of the system. Both parameters are measurable as phase noise spectra. The intrinsic parameters PInt and G can be inferred by manipulating the stimulus and observing response of the PLL. This model quantifies the PLL intrinsic noise and noise transfer without any knowledge of the circuits. 3. Proposed Methodology and Data For the lumped-component linear noise model, knowledge of PInt and G allows the prediction of POut for any PRef. The two quantities PInt and G can be found by careful manipulation of PRef and observation of POut using a bench-top characterization setup shown in Figure 3. The PLL under test is a transmitter (Tx) PLL for a transceiver device. The reference clock generator is an Agilent 81134A externally clocked by an rf generator (Agilent 8257D) to minimize intrinsic noise. Controlled levels of phase noise are added to the reference clock by applying white voltage noise (NoiseCom UFX 9836) to the time delay input of the clock generator. The time delay converts input voltages into timing offsets in the clock signal with a ratio of 250 ps/V and a bandwidth of 200 MHz. Table 1 shows the relevant settings of the Tx PLL. RF Gen (Agilent 8257D) Clock Gen (Agilent 81134A) Noise Source (NoiseCom UFX9836) Phase Noise Analyzer (Agilent E4440A) Ext Clk Time Delay Out Out